Due to our consultancy activities TES engineers can provide a wide range of know-how in different markets, tools, methods and all scales of projects.
We have performed full developments of large digital multi-million gate Designs as well as miscellaneous kinds of mixed-signal and RF ASICs.
- From Spec. to Validation.
- RTL design with VHDL, Verilog, SystemVerilog, SystemC.
- Verification/Simulation with Modelsim, Incisive, VCS and others.
- Verification flows via modelling (C/C++/SystemC), proprietary standard, OVM/UVM.
- Synthesis/P&R flows with Cadence or Synopsis.
- Full Backend Flow including DRV, LVS and STA.
- DFT, Test Pattern generation, Fault analysis.
- FPGA prototyping.
- Full lab validation.
- Supply Chain.
We can handle the complete Tape-Out flow with all major ASIC vendors and can take over all needs of validation and communication towards production and test house.
TES is proud to name all major players on the silicon market as customers and therefore can provide an extremely wide range of methods towards the customer.