CDC Customizable Display Controllers - Overview
CDC is a fully Customizable Display Controller IP supporting the OpenWF display API specification. A number of features can be configured at synthesis time and programmed at run time. The display controller can be applied to e.g. FPGA systems with a resource optimized, application specific feature configuration or to ASIC projects applying a more generic feature set and thus more flexibility
The main functionality of CDC is reading images (layers) from memory, combining them on-the-fly e.g. by blending, cropping and windowing and generating a video output stream of the combined image.
On the output the controller provides a digital RGB signal with video data and signals for horizontal/vertical blank and synchronization. Optionally a digital component (YCBCR) output signal can be configured at synthesis time. The CDC’s output typically is then connected with the physical display output block like an HDMI our LVDS IP block or a Video DAC.
Scope of Delivery & Requirements
The D/AVE 2D core is available in two different versions. A ‘standard’ version named D/AVE 2D-TS and ‘light’ version named D/AVE 2D-TL. The major differences between both cores are that D/AVE 2D-TL is not supporting performance counting and is slower in terms of pixel processing. The D/AVE 2D-TS render pipeline produces one pixel per cycle, D/AVE 2D-TL needs four cycles for a pixel.
In the ALTERA Qsys™ environment D/AVE uses Avalon bus interface, it is tested on the device families Cyclone II, Cyclone III and Stratix. An AMBA AHB/APB bus interface is also available.
- Quartus II 10.1
- NIOS II EDS 10.1
- Nios II Development Kit, Cyclone III FPGA Starter Kit (3C25)
In this example, images from two video cameras are transferred to frame buffers in memory using two CVIs (Configurable Video Input controller, another TES IP), while the internal CPU/GPU generates GUI elements to be used in the displayed image in a 3rd framebuffer. The CDC clips and scales the image stored in layer 2 and blends it with the main image on layer 1, using windowing to display it in the upper left corner, while adding some transparency to keep the occupied part of the main image visible. The GUI element is blended into the lower left corner, again using the transparency feature of the CDC.
The resulting image is transferred to a Video PHY block, which provides a standard video display interface (e.g. SVGA, DVI, HDMI) suitable for the attached monitor.
Based on a highly modular architecture the CDC-Family offers a wide range of features from CDC-200 providing basic functionality with each family member offering additional configurable feature extensions up to the flag-ship CDC-500 which supports output image rotation. The features are configurable at design-time and can be controlled at run-time via an simple basic driver for register agnostic control or a Khronos standard OpenWF Display API driver.
The following table outlines the set of configurable features for all CDC-Family members:
|RGB/Greyscale Input Formats||x||x||x||x|
|Mirroring (H & V)||x||x||x|
|YCBCR Input Formats)||x||x||x|
|YCBCR Output Formats||x||x|
|Layer Blending Order||x||x|
|Single Frame Mode||x||x|
|Dual CPU Support||x||x|
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