Hardware IP cores for ASICs and FPGAs and Software IP cores for micro-processors
TES offers a variety of graphics rendering IP cores from 2D GPUs, e.g. for ultra-low power devices and state-of-the-art user interfaces in mass-market consumer applications, up to powerful 3D GPUs for premium graphics applications on Ultra-HD displays. With a history of more than 10 years our IPs are field proven in automotive and mass market consumer applications.
What makes TES IPs special and is reflected by our business models is the extremely high level of customizability of our IPs: All our IPs are based on modular, customizable designs and are highly adaptable to meet our customers specific needs concerning functionality, performance, footprint and special system requirements such as functional safety.
Together with our IP cores we provide high-professional engineering support for IP customization, integration, driver-porting and graphics application development.
Hardware Rendering IP Cores
IP cores delivered in VHDL for use in FPGAs, ASICs and SOCs:
2D graphics rendering engine with powerful BLIT functions and vector graphics features.
<100k gates, < 35kBits memory
~10 k LEs on, Intel PSG FPGAs
Lite Variant: Fully feature compatible variant of D/AVE 2D configured for minimum footprint on cost of performance.
<60k gates, < 20kBits memory
~6 k LEs on, Intel PSG FPGAs
Feature-rich 2D/3D graphics rendering engine optimized for highest performance targeting high-end graphics on up to 4k x 4k displays.
Full OpenVG 1.1 compliancy. Provides hardware multithreading support and system safety features.
250-500k gates, 80-200kBits memory
~30-50k LEs on Intel PSG FPGAs
3D graphics rendering engine with OpenGL ES 1.1 and OpenVG 1.01 API. Offers high performance at 8M tri/sec, Edge-based anti-aliasing.
~1200k gates, 200-400kBits memory
~90 k LEs on Intel PSG FPGAs
3D graphics rendering engine, fully OpenGl ES 2.0 compliant and prepared for OpenGL ES 3.x and VULKAN
Targeting premium graphics on up to 4k x 4k displays. Highly scalable (e.g. #Shader Units and ALUs per Shader Unit) and with performance/footprint balance optimized for FPGAs and small MPUs
Prepared for OpenGL SC 2.0 support for safety critical applications
Footprint strongly depends on configuration (from <100k LEs up to some 100k LEs on IntelPSG FPGAs
Performance and feature comparison of the hardware rendering IPs
(click to enlarge)
Highly portable and modular software rendering cores for MPUs and DSPs delivered as library or source code
- Highly portable C++ 2D/3D graphics IP core targeting high quality real-time graphics on embedded devices with single 32bit CPU cores like ARM, MIPS, xscale, x86, PowerPC and SH-4.
- RAM ~16KB, ROM150-600KB
- Feature-rich ANSI-C 2D/3D graphics IP core for small footprint Microcontrollers & CPU+DSP systems with ANSI C API and optional OpenGL ES 1.1 subset API.
- ROM 50-400KB