D/AVE 2D is a Hardware IP Core, optimized for easy integration into FPGAs and ASICs. Focus of D/AVE 2D is to provide cost efficient high quality vector graphics with subpixel processing and an extended anti-aliasing functionality.
D/AVE 2D has been developed for all applications that benefit from high quality vector graphics. Examples are Navigation, Dashboard and OSD Applications in the Automotive and Aviation area.
- High Quality Antialiasing
- Subpixel accurate rendering
- Resolutions up to 2048x2048
- Extended Rendering Primitives supported in Hardware
- LINES with arbitrary width, round and truncated endpoints, alpha gradients, soft edges
- POLYGONS, triangles and quadrangles with support of alpha gradients, soft edges and per edge control for antialiasing
- CIRCLES and ELLIPSES, support of all conic sections, filled or with arbitrary width, arcs of 0°-360°, soft edges, alpha gradients
- QUADRATIC and CUBIC BÉZIER’S (Attribute: Color) support of arbitrary width, round or truncated endpoints, alpha gradients
- Block Image Tranfers (BLIT) 16 Blending Modes
- Patterns and Gradients with Alpha Channel on all Primitives
- Textures up to 2048x1024
- Bilinear Filtering
- Render to Texture
- Texture Blending
- No Cost Hardware Clipping
- Flexible Input and Output Formats for Framebuffer and Textures
- Very Small Core Size
- Easy Core Integration
- Fully Reentrant Driver
Scope of Delivery & Requirements
The D/AVE 2D core is available in two different versions. A ‘standard’ version named D/AVE 2D-TS and ‘light’ version named D/AVE 2D-TL. The major differences between both cores are that D/AVE 2D-TL is not supporting performance counting and is slower in terms of pixel processing. The D/AVE 2D-TS render pipeline produces one pixel per cycle, D/AVE 2D-TL needs four cycles for a pixel.
In the ALTERA Qsys™ environment D/AVE uses Avalon bus interface, it is tested on the device families Cyclone II, Cyclone III and Stratix. An AMBA AHB/APB bus interface is also available.
- Quartus II 10.1
- NIOS II EDS 10.1
- Nios II Development Kit, Cyclone III FPGA Starter Kit (3C25)
Contents of D/AVE 2D EvalKit
- D/AVE 2D Qsys component, run-time limited
- Precompiled FPGA configurations (.sof files) for Altera Development Kits
- Precompiled demo applications for Altera Development Kits
- Example Quartus II projects for hardware integration of D/AVE 2D
- Example Nios II IDE projects for software integration of D/AVE
- D/AVE 2D API documentation
- Demo source code for showing usage of D/AVE 2D API
- Nios II libraries of D/AVE 2D driver
- Nios II sources of lowlevel driver
- Windows software emulation of D/AVE 2D (SoftDAVE)
Overview D/AVE 2D Lite
D/AVE 2D-Lite is the ultra low-cost variant of configured for smallest footprint on cost of performance and some features.
Limitations of D/AVE 2D-Lite compared with D/AVE 2D
D/AVE 2D-Lite needs 4 cycles per pixel while D/AVE 2D needs only 1 cycle (except in case of texture filtering). Since this peak performance cannot be fully reached in most use cases anyway due to bus bandwidth and latency limitations, the performance difference from application point of view is in the range of a factor of 2-3 instead of 4.
- Sub-byte texture formats (1,2 and 4bpp) as well as CLUT formats are not available in D/AVE 2D-Lite.
- Color-keying is not available in D/AVE 2D-Lite.
- Run Length Encoded textures are not available in the current version of D/AVE 2D-Lite.
- Alpha channel blending in the blend unit is not available in the current version of D/AVE 2D-Lite.