TES Portfolio of Video and Graphics (GPU) IPs

TES offers a portfolio of video I/O, video-processing and grphics renering (GPU) IP cores including software drivers allowing to build a complete video-input, graphics and display output subsystem. Our IPs are targeted at ASICs (MCUs, MPUs) and FPGAs. 

• 2D, 2.5D, 3D GPUs and vector graphics rendering cores - Overview
• CDC Display Controller IP Core Family
• CVI Video Input Controller IP Core
• Warping Engine Image Transformation IP Core